1. Field of the Invention
The present invention generally relates to the fabrication of microelectronic integrated circuit devices in semiconductive materials, and more specifically to a semiconductive arrangement having dissimilar, laterally spaced layer structures which enable the fabrication of dissimilar devices therein.
2. Description of the Related Art
It is desirable in the production of microelectronic circuits to integrate as many devices as possible onto a single integrated circuit chip. This goal is made difficult by the fact that the many dissimilar devices which have been developed and are theoretically available for use often have conflicting characteristics. One type of device may function optimally when fabricated in a certain material structure, whereas another type of device may be completely inoperative in the same material structure.
The integration of complementary heterojunction bipolar transistors (HBTs) is a primary example, in that the PNP and NPN transistors have dissimilar epitaxial structures. However, the problem is common to integration of many other types of dissimilar devices, such as varactor diodes and HBTs, semiconductor lasers and HBTs, photodiodes and HBTs, various devices with field effect transistors (FETs) and high electron mobility transistors (HEMTs), etc.
Previous approaches to the integration of dissimilar devices include fabrication of the devices in a vertically stacked arrangement as disclosed in an article entitled "Optoelectronic Integrated Receivers on InP Substrates by Organometallic Vapor Phase Epitaxy", by G. Sasaki et al, in Journal of Lightwave Technology, Vol. 7, no. 10, pp. 1510-1513 (Oct. 1989). However, this type of process is disadvantageous in that it requires fine line photolithography, etching, contact metallization, planarization, and interconnect metallization over a wafer which has a large elevation difference between the lowest point (usually a semi-insulating substrate isolating the lower devices), and the highest point (usually the top electrode of the upper devices). These height differences can make processing extremely difficult or even impossible.
A second approach requires selective area epitaxial growth of at least one of the epitaxial structures. An example is disclosed in an article entitled "GaAs/GaAlAs Selective MOCVD Epitaxy and Planar Ion-Implantation Technique for Complex Integrated Optoelectronic Circuit Applications", by M. Kim et al, in IEEE Electron Device Letters, vol. EDL-5, no. 8, pp. 306-309 (Aug. 1984). This technique is disadvantageous in that it is difficult and time consuming, and further in that it jeopardizes the quality of the selective area epitaxial material.
A relevant variation on the selective area epitaxy approach is disclosed in an article entitled "A Novel Planarization Technique for Optoelectronic Integrated Circuits and Its Application to a Monolithic AlGaAs/GaAs p-i-n FET", by S. Miura et al, in IEEE Transactions on Electron Devices, vol. ED-34, no. 2, pp. 241-246 (Feb. 1987). This reference teaches how to embed a device in a well formed in the surface of a substrate or wafer, and planarize the surface of the device with the surface of the surrounding substrate. Subsequent to fabrication of the embedded device, selective area epitaxy is used to form epitaxial layer structures on other areas of the substrate for fabrication of additional devices.